The Solutions Group high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Opportunities
SNPS is the world number one IP provider. To be trained and developed by many experts from around the world and talented Viet Nam engineering team
Professional, innovative, fair and fun working environment. Strong culture company.
Competitive salary and benefit. Dedicated support from company for health: Insurance, Sport clubs: Football, Table-tennis, Badminton, Yoga, Zumba …
Dedicated support from company for team building, social activities: Team trip, Family Day…
Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
Chance to work with bleeding edge technologies that enable Data Center, AI/ML, 5G applications.
Clear career path of self-development to either Technical Expert or Design Leader/Manager
Job Descriptions
Create DFT specification based on architecture specification from Front End team
Perform DFT design rule check and scan insertion
Perform ATPG and coverage debugging
Perform DFT verification with and without timing back annotation.
Support Customer in bringing up DFT pattern in Silicon.
Yêu Cầu Công Việc
Requirements:
Good knowledge of DFT architecture
Familiar with DFT flow, including DFT design, implementation, verification, pattern, and testing
Experience in Scan/BSD/LBIST
Familiar with scripting languages, such as TCL, Perl, and Verilog.
Good knowledge of synthesis, timing closure and silicon test
Good English/communication skills and willingness to work with a global team
Preferred Experience:
Ideally, should have 2+ years of DFT design background and have led teams on implementation/verification of Design-for-Test logic on a few designs
Knowledge of synthesis/ timing/ constraint/ layout is a plus
Familiar with pattern debugging, failure analysis, and yield improvement
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
